simulavr  1.1.0
Class Hierarchy

Go to the graphical class hierarchy

This inheritance list is sorted roughly, but not completely, alphabetically:
[detail level 1234]
 CAnalogSignalChange
 CAnalogValueImplements "real" analog value as float
 CApplication
 CAvrFactoryProduces AVR devices
 CAvrFusesSupport for fuse bits
 CAvrLockBitsSupport for lock bits
 CDecLong
 CDecodedInstructionBase class of core instruction
 CDumper
 CDumpManager
 CExternalType
 CFunktor
 CGdbServerSocketInterface for server socket wrapper
 CHardware
 CHasPinNotifyFunction
 CHexChar
 CHexShort
 CHWARefReference source for ADC (base class)
 CHWPcicrApi
 CHWPcifrApi
 CHWPcirMaskApi
 CHWPcmskApi
 CHWPcmskPinApi
 CHWSreg_bool
 CHWStackImplements a stack register with stack logic
 CHWTimerTinyX5_SyncRegHelper class to simulate transfer of register values from bus area to timer async area
 CICaptureSourceClass, which provides input capture source for 16bit timers
 CIOSpecialRegClientInterface class to connect hardware units to control registers
 CIRQLineRepresents a timer interrupt line, Frontend for timer interrupts
 CIrqStatisticEntry
 CIrqStatisticPerVector
 Cstd::map< K, T >STL class
 CMemoryHold a memory block and symbol informations
 CPinPin class, handles input and output to external parts
 CPinAtPort
 CPrescalerMultiplexerPrescalerMultiplexer without external count pin
 CPrintable
 CRWMemoryMemberMember of any memory area in an AVR device
 CSimulationMember
 CSocket
 CSystemClockClass to store and manage the central simulation time
 CSystemConsoleHandlerClass, that handle messages to console and also exit/abort calls
 CThread
 CThreadList
 CTimerEventListener
 CTimerTinyX5_OCRPWM output unit for timer 1 on ATtiny25/45/85
 CTraceValue
 CTraceValueRegisterBuild a register for TraceValue's
 Cstd::vector< T >STL class