simulavr  1.1.0
atmega2560base.cpp
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1  /*
2  ****************************************************************************
3  *
4  * simulavr - A simulator for the Atmel AVR family of microcontrollers.
5  * Copyright (C) 2001, 2002, 2003 Klaus Rudolph
6  * Copyright (C) 2015 Christian Taedcke
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21  *
22  ****************************************************************************
23  */
24 #include "atmega2560base.h"
25 
26 #include "irqsystem.h"
27 #include "hwstack.h"
28 #include "hweeprom.h"
29 #include "hwwado.h"
30 #include "hwsreg.h"
31 #include "avrerror.h"
32 #include "avrfactory.h"
33 
37 
39  delete usart3;
40  delete usart2;
41  delete usart1;
42  delete usart0;
43  delete wado;
44  delete spi;
45  delete acomp;
46  delete ad;
47  delete aref;
48  delete admux;
49  delete gpior2_reg;
50  delete gpior1_reg;
51  delete gpior0_reg;
52  delete timer5;
53  delete inputCapture5;
54  delete timerIrq5;
55  delete timer4;
56  delete inputCapture4;
57  delete timerIrq4;
58  delete timer3;
59  delete inputCapture3;
60  delete timerIrq3;
61  delete timer2;
62  delete timerIrq2;
63  delete timer1;
64  delete inputCapture1;
65  delete timerIrq1;
66  delete timer0;
67  delete timerIrq0;
68  delete extirqpc;
69  delete pcmsk2_reg;
70  delete pcmsk1_reg;
71  delete pcmsk0_reg;
72  delete pcifr_reg;
73  delete pcicr_reg;
74  delete extirq;
75  delete eifr_reg;
76  delete eimsk_reg;
77  delete eicra_reg;
78  delete eicrb_reg;
79  delete eind;
80  delete rampz;
81  delete osccal_reg;
82  delete clkpr_reg;
83  delete stack;
84  delete eeprom;
85  delete irqSystem;
86  delete spmRegister;
87 }
88 
90  unsigned flash_bytes,
91  unsigned ee_bytes,
92  unsigned nrww_start):
93  AvrDevice(0x200 - 32, // I/O space size (above ALU registers)
94  ram_bytes, // RAM size
95  0, // External RAM size
96  flash_bytes, // Flash Size
97  3), // PC size
98  porta(this, "A", true),
99  portb(this, "B", true),
100  portc(this, "C", true),
101  portd(this, "D", true),
102  porte(this, "E", true),
103  portf(this, "F", true),
104  portg(this, "G", true),
105  porth(this, "H", true),
106  portj(this, "J", true),
107  portk(this, "K", true),
108  portl(this, "L", true),
109  gtccr_reg(&coreTraceGroup, "GTCCR"),
110  assr_reg(&coreTraceGroup, "ASSR"),
111  prescaler1(this, "1", &gtccr_reg, 0, 7),
112  prescaler2(this, "2", PinAtPort(&portg, 4), &assr_reg, 5, &gtccr_reg, 1, 7),
113  premux0(&prescaler1, PinAtPort(&portd, 7)),
114  premux1(&prescaler1, PinAtPort(&portd, 6)),
115  premux2(&prescaler2),
116  premux3(&prescaler1, PinAtPort(&porte, 6)),
117  premux4(&prescaler1, PinAtPort(&porth, 7)),
118  premux5(&prescaler1, PinAtPort(&portl, 2))
119 {
120  flagELPMInstructions = true;
121  flagEIJMPInstructions = true;
122  fuses->SetFuseConfiguration(19, 0xff9962);
123  fuses->SetBootloaderConfig(nrww_start, 0x1000, 9, 8);
124  spmRegister = new FlashProgramming(this, 128, nrww_start, FlashProgramming::SPM_MEGA_MODE);
125 
126  irqSystem = new HWIrqSystem(this, 4, 57);
127 
128  eeprom = new HWEeprom(this, irqSystem, ee_bytes, 30, HWEeprom::DEVMODE_EXTENDED);
129  stack = new HWStackSram(this, 16, true);
130  clkpr_reg = new CLKPRRegister(this, &coreTraceGroup);
132 
133  rampz = new AddressExtensionRegister(this, "RAMPZ", 2);
134  eind = new AddressExtensionRegister(this, "EIND", 1);
135 
136  eicra_reg = new IOSpecialReg(&coreTraceGroup, "EICRA");
137  eicrb_reg = new IOSpecialReg(&coreTraceGroup, "EICRB");
138  eimsk_reg = new IOSpecialReg(&coreTraceGroup, "EIMSK");
139  eifr_reg = new IOSpecialReg(&coreTraceGroup, "EIFR");
141  extirq->registerIrq(1, 0, new ExternalIRQSingle(eicra_reg, 0, 2, GetPin("D0")));
142  extirq->registerIrq(2, 1, new ExternalIRQSingle(eicra_reg, 2, 2, GetPin("D1")));
143  extirq->registerIrq(3, 2, new ExternalIRQSingle(eicra_reg, 4, 2, GetPin("D2")));
144  extirq->registerIrq(4, 3, new ExternalIRQSingle(eicra_reg, 6, 2, GetPin("D3")));
145  extirq->registerIrq(5, 4, new ExternalIRQSingle(eicrb_reg, 0, 2, GetPin("E4")));
146  extirq->registerIrq(6, 5, new ExternalIRQSingle(eicrb_reg, 2, 2, GetPin("E5")));
147  extirq->registerIrq(7, 6, new ExternalIRQSingle(eicrb_reg, 4, 2, GetPin("E6")));
148  extirq->registerIrq(8, 7, new ExternalIRQSingle(eicrb_reg, 6, 2, GetPin("E7")));
149 
150  pcicr_reg = new IOSpecialReg(&coreTraceGroup, "PCICR");
151  pcifr_reg = new IOSpecialReg(&coreTraceGroup, "PCIFR");
152  pcmsk0_reg = new IOSpecialReg(&coreTraceGroup, "PCMSK0");
153  pcmsk1_reg = new IOSpecialReg(&coreTraceGroup, "PCMSK1");
154  pcmsk2_reg = new IOSpecialReg(&coreTraceGroup, "PCMSK2");
157 
158  Pin* pcmask1PinList[] = {
159  GetPin("E0"), //PCINT8
160  GetPin("J0"), //PCINT9
161  GetPin("J1"), //PCINT10
162  GetPin("J2"), //PCINT11
163  GetPin("J3"), //PCINT12
164  GetPin("J4"), //PCINT13
165  GetPin("J5"), //PCINT14
166  GetPin("J6") //PCINT15
167  };
168 
169  extirqpc->registerIrq(10, 1, new ExternalIRQPort(pcmsk1_reg, pcmask1PinList));
171 
172  timerIrq0 = new TimerIRQRegister(this, irqSystem, 0);
173  timerIrq0->registerLine(0, IRQLine("TOV0", 23));
174  timerIrq0->registerLine(1, IRQLine("OCF0A", 21));
175  timerIrq0->registerLine(2, IRQLine("OCF0B", 22));
176 
177  timer0 = new HWTimer8_2C(this,
178  &premux0,
179  0,
180  timerIrq0->getLine("TOV0"),
181  timerIrq0->getLine("OCF0A"),
182  PinAtPort(&portb, 7),
183  timerIrq0->getLine("OCF0B"),
184  PinAtPort(&portg, 5));
185 
186  timerIrq1 = new TimerIRQRegister(this, irqSystem, 1);
187  timerIrq1->registerLine(0, IRQLine("TOV1", 20));
188  timerIrq1->registerLine(1, IRQLine("OCF1A", 17));
189  timerIrq1->registerLine(2, IRQLine("OCF1B", 18));
190  timerIrq1->registerLine(3, IRQLine("OCF1C", 19));
191  timerIrq1->registerLine(5, IRQLine("ICF1", 16));
192 
194  timer1 = new HWTimer16_3C(this,
195  &premux1,
196  1,
197  timerIrq1->getLine("TOV1"),
198  timerIrq1->getLine("OCF1A"),
199  PinAtPort(&portb, 5),
200  timerIrq1->getLine("OCF1B"),
201  PinAtPort(&portb, 6),
202  timerIrq1->getLine("OCF1C"),
203  PinAtPort(&portb, 7),
204  timerIrq1->getLine("ICF1"),
205  inputCapture1);
206 
207  timerIrq2 = new TimerIRQRegister(this, irqSystem, 2);
208  timerIrq2->registerLine(0, IRQLine("TOV2", 15));
209  timerIrq2->registerLine(1, IRQLine("OCF2A", 13));
210  timerIrq2->registerLine(2, IRQLine("OCF2B", 14));
211 
212  timer2 = new HWTimer8_2C(this,
213  &premux2,
214  2,
215  timerIrq2->getLine("TOV2"),
216  timerIrq2->getLine("OCF2A"),
217  PinAtPort(&portb, 4),
218  timerIrq2->getLine("OCF2B"),
219  PinAtPort(&porth, 6));
220 
221  timerIrq3 = new TimerIRQRegister(this, irqSystem, 3);
222  timerIrq3->registerLine(0, IRQLine("TOV3", 35));
223  timerIrq3->registerLine(1, IRQLine("OCF3A", 32));
224  timerIrq3->registerLine(2, IRQLine("OCF3B", 33));
225  timerIrq3->registerLine(3, IRQLine("OCF3C", 34));
226  timerIrq3->registerLine(5, IRQLine("ICF3", 31));
227 
229  timer3 = new HWTimer16_3C(this,
230  &premux3,
231  3,
232  timerIrq3->getLine("TOV3"),
233  timerIrq3->getLine("OCF3A"),
234  PinAtPort(&porte, 3),
235  timerIrq3->getLine("OCF3B"),
236  PinAtPort(&porte, 4),
237  timerIrq3->getLine("OCF3C"),
238  PinAtPort(&porte, 5),
239  timerIrq3->getLine("ICF3"),
240  inputCapture3);
241 
242  timerIrq4 = new TimerIRQRegister(this, irqSystem, 4);
243  timerIrq4->registerLine(0, IRQLine("TOV4", 45));
244  timerIrq4->registerLine(1, IRQLine("OCF4A", 42));
245  timerIrq4->registerLine(2, IRQLine("OCF4B", 43));
246  timerIrq4->registerLine(3, IRQLine("OCF4C", 44));
247  timerIrq4->registerLine(5, IRQLine("ICF4", 41));
248 
250  timer4 = new HWTimer16_3C(this,
251  &premux4,
252  4,
253  timerIrq4->getLine("TOV4"),
254  timerIrq4->getLine("OCF4A"),
255  PinAtPort(&porth, 3),
256  timerIrq4->getLine("OCF4B"),
257  PinAtPort(&porth, 4),
258  timerIrq4->getLine("OCF4C"),
259  PinAtPort(&porth, 5),
260  timerIrq4->getLine("ICF4"),
261  inputCapture4);
262 
263  timerIrq5 = new TimerIRQRegister(this, irqSystem, 5);
264  timerIrq5->registerLine(0, IRQLine("TOV5", 50));
265  timerIrq5->registerLine(1, IRQLine("OCF5A", 47));
266  timerIrq5->registerLine(2, IRQLine("OCF5B", 48));
267  timerIrq5->registerLine(3, IRQLine("OCF5C", 49));
268  timerIrq5->registerLine(5, IRQLine("ICF5", 46));
269 
271  timer5 = new HWTimer16_3C(this,
272  &premux5,
273  5,
274  timerIrq5->getLine("TOV5"),
275  timerIrq5->getLine("OCF5A"),
276  PinAtPort(&portl, 3),
277  timerIrq5->getLine("OCF5B"),
278  PinAtPort(&portl, 4),
279  timerIrq5->getLine("OCF5C"),
280  PinAtPort(&portl, 5),
281  timerIrq5->getLine("ICF5"),
282  inputCapture5);
283 
284  gpior0_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR0");
285  gpior1_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR1");
286  gpior2_reg = new GPIORegister(this, &coreTraceGroup, "GPIOR2");
287 
288  admux = new HWAdmuxM2560(this, &portf.GetPin(0), &portf.GetPin(1), &portf.GetPin(2),
289  &portf.GetPin(3), &portf.GetPin(4), &portf.GetPin(5),
290  &portf.GetPin(6), &portf.GetPin(7), &portk.GetPin(0),
291  &portk.GetPin(1), &portk.GetPin(2), &portk.GetPin(3),
292  &portk.GetPin(4), &portk.GetPin(5), &portk.GetPin(6),
293  &portk.GetPin(7));
294  aref = new HWARef4(this, HWARef4::REFTYPE_BG3);
295  ad = new HWAd(this, HWAd::AD_M2560, irqSystem, 29, admux, aref);
296 
297  acomp = new HWAcomp(this, irqSystem, PinAtPort(&porte, 2), PinAtPort(&porte, 3), 28, ad, timer1);
298 
299  spi = new HWSpi(this,
300  irqSystem,
301  PinAtPort(&portb, 2), // MOSI
302  PinAtPort(&portb, 3), // MISO
303  PinAtPort(&portb, 1), // SCK
304  PinAtPort(&portb, 0), // /SS
305  24, // irqvec
306  true);
307 
308  wado = new HWWado(this);
309 
310  usart0 = new HWUsart(this,
311  irqSystem,
312  PinAtPort(&porte, 1), // TXD0
313  PinAtPort(&porte, 0), // RXD0
314  PinAtPort(&porte, 2), // XCK0
315  25, // (26) RX complete vector
316  26, // (27) UDRE vector
317  27); // (28) TX complete vector
318 
319  usart1 = new HWUsart(this,
320  irqSystem,
321  PinAtPort(&portd, 3), // TXD1
322  PinAtPort(&portd, 2), // RXD1
323  PinAtPort(&portd, 5), // XCK1
324  36, // (37) RX complete vector
325  37, // (38) UDRE vector
326  38, // (39) TX complete vector
327  1); // instance_id for tracking in UI
328 
329  usart2 = new HWUsart(this,
330  irqSystem,
331  PinAtPort(&porth, 1), // TXD2
332  PinAtPort(&porth, 0), // RXD2
333  PinAtPort(&porth, 2), // XCK2
334  51, // (52) RX complete vector
335  52, // (53) UDRE vector
336  53, // (54) TX complete vector
337  2); // instance_id for tracking in UI
338 
339  usart3 = new HWUsart(this,
340  irqSystem,
341  PinAtPort(&portj, 1), // TXD3
342  PinAtPort(&portj, 0), // RXD3
343  PinAtPort(&portj, 2), // XCK3
344  54, // (55) RX complete vector
345  55, // (56) UDRE vector
346  56, // (57) TX complete vector
347  3); // instance_id for tracking in UI
348 
349  rw[0x136]= & usart3->udr_reg;
350  rw[0x135]= & usart3->ubrrhi_reg;
351  rw[0x134]= & usart3->ubrr_reg;
352  // 0x133 reserved
353  rw[0x132]= & usart3->ucsrc_reg;
354  rw[0x131]= & usart3->ucsrb_reg;
355  rw[0x130]= & usart3->ucsra_reg;
356  // 0x12F and 0x12E reserved
357  rw[0x12D]= & timer5->ocrc_h_reg;
358  rw[0x12C]= & timer5->ocrc_l_reg;
359  rw[0x12B]= & timer5->ocrb_h_reg;
360  rw[0x12A]= & timer5->ocrb_l_reg;
361  rw[0x129]= & timer5->ocra_h_reg;
362  rw[0x128]= & timer5->ocra_l_reg;
363  rw[0x127]= & timer5->icr_h_reg;
364  rw[0x126]= & timer5->icr_l_reg;
365  rw[0x125]= & timer5->tcnt_h_reg;
366  rw[0x124]= & timer5->tcnt_l_reg;
367  // 0x123 reserved
368  rw[0x122]= & timer5->tccrc_reg;
369  rw[0x121]= & timer5->tccrb_reg;
370  rw[0x120]= & timer5->tccra_reg;
371  // 0x10C - 0x11F reserved
372  rw[0x10B]= & portl.port_reg;
373  rw[0x10A]= & portl.ddr_reg;
374  rw[0x109]= & portl.pin_reg;
375  rw[0x108]= & portk.port_reg;
376  rw[0x107]= & portk.ddr_reg;
377  rw[0x106]= & portk.pin_reg;
378  rw[0x105]= & portj.port_reg;
379  rw[0x104]= & portj.ddr_reg;
380  rw[0x103]= & portj.pin_reg;
381  rw[0x102]= & porth.port_reg;
382  rw[0x101]= & porth.ddr_reg;
383  rw[0x100]= & porth.pin_reg;
384  // 0xD7 - 0xFF reserved
385  rw[0xD6]= & usart2->udr_reg;
386  rw[0xD5]= & usart2->ubrrhi_reg;
387  rw[0xD4]= & usart2->ubrr_reg;
388  // 0xD3 reserved
389  rw[0xD2]= & usart2->ucsrc_reg;
390  rw[0xD1]= & usart2->ucsrb_reg;
391  rw[0xD0]= & usart2->ucsra_reg;
392  // 0xCF reserved
393  rw[0xCE]= & usart1->udr_reg;
394  rw[0xCD]= & usart1->ubrrhi_reg;
395  rw[0xCC]= & usart1->ubrr_reg;
396  // 0xCB reserved
397  rw[0xCA]= & usart1->ucsrc_reg;
398  rw[0xC9]= & usart1->ucsrb_reg;
399  rw[0xC8]= & usart1->ucsra_reg;
400  // 0xC7 reserved
401  rw[0xC6]= & usart0->udr_reg;
402  rw[0xC5]= & usart0->ubrrhi_reg;
403  rw[0xC4]= & usart0->ubrr_reg;
404  // 0xC3 reserved
405  rw[0xC2]= & usart0->ucsrc_reg;
406  rw[0xC1]= & usart0->ucsrb_reg;
407  rw[0xC0]= & usart0->ucsra_reg;
408  // 0xBF reserved
409  // 0xBE reserved
416  // 0xB7 reserved
417  rw[0xB6]= & assr_reg;
418  // 0xB5 reserved
419  rw[0xB4]= & timer2->ocrb_reg;
420  rw[0xB3]= & timer2->ocra_reg;
421  rw[0xB2]= & timer2->tcnt_reg;
422  rw[0xB1]= & timer2->tccrb_reg;
423  rw[0xB0]= & timer2->tccra_reg;
424  // 0xAE and 0xAF reserved
425  rw[0xAD]= & timer4->ocrc_h_reg;
426  rw[0xAC]= & timer4->ocrc_l_reg;
427  rw[0xAB]= & timer4->ocrb_h_reg;
428  rw[0xAA]= & timer4->ocrb_l_reg;
429  rw[0xA9]= & timer4->ocra_h_reg;
430  rw[0xA8]= & timer4->ocra_l_reg;
431  rw[0xA7]= & timer4->icr_h_reg;
432  rw[0xA6]= & timer4->icr_l_reg;
433  rw[0xA5]= & timer4->tcnt_h_reg;
434  rw[0xA4]= & timer4->tcnt_l_reg;
435  // 0xA3 reserved
436  rw[0xA2]= & timer4->tccrc_reg;
437  rw[0xA1]= & timer4->tccrb_reg;
438  rw[0xA0]= & timer4->tccra_reg;
439  // 0x9E and 0x9F reserved
440  rw[0x9D]= & timer3->ocrc_h_reg;
441  rw[0x9C]= & timer3->ocrc_l_reg;
442  rw[0x9B]= & timer3->ocrb_h_reg;
443  rw[0x9A]= & timer3->ocrb_l_reg;
444  rw[0x99]= & timer3->ocra_h_reg;
445  rw[0x98]= & timer3->ocra_l_reg;
446  rw[0x97]= & timer3->icr_h_reg;
447  rw[0x96]= & timer3->icr_l_reg;
448  rw[0x95]= & timer3->tcnt_h_reg;
449  rw[0x94]= & timer3->tcnt_l_reg;
450  // 0x93 reserved
451  rw[0x92]= & timer3->tccrc_reg;
452  rw[0x91]= & timer3->tccrb_reg;
453  rw[0x90]= & timer3->tccra_reg;
454  // 0x8E and 0x8F reserved
455  rw[0x8D]= & timer1->ocrc_h_reg;
456  rw[0x8C]= & timer1->ocrc_l_reg;
457  rw[0x8B]= & timer1->ocrb_h_reg;
458  rw[0x8A]= & timer1->ocrb_l_reg;
459  rw[0x89]= & timer1->ocra_h_reg;
460  rw[0x88]= & timer1->ocra_l_reg;
461  rw[0x87]= & timer1->icr_h_reg;
462  rw[0x86]= & timer1->icr_l_reg;
463  rw[0x85]= & timer1->tcnt_h_reg;
464  rw[0x84]= & timer1->tcnt_l_reg;
465  // 0x83 reserved
466  rw[0x82]= & timer1->tccrc_reg;
467  rw[0x81]= & timer1->tccrb_reg;
468  rw[0x80]= & timer1->tccra_reg;
472  rw[0x7C]= & ad->admux_reg;
473  rw[0x7B]= & ad->adcsrb_reg;
474  rw[0x7A]= & ad->adcsra_reg;
475  rw[0x79]= & ad->adch_reg;
476  rw[0x78]= & ad->adcl_reg;
477  // 0x76, 0x77 reserved
480  rw[0x73]= & timerIrq5->timsk_reg;
481  rw[0x72]= & timerIrq4->timsk_reg;
482  rw[0x71]= & timerIrq3->timsk_reg;
483  rw[0x70]= & timerIrq2->timsk_reg;
484  rw[0x6F]= & timerIrq1->timsk_reg;
485  rw[0x6E]= & timerIrq0->timsk_reg;
486  rw[0x6D]= pcmsk2_reg;
487  rw[0x6C]= pcmsk1_reg;
488  rw[0x6B]= pcmsk0_reg;
489  rw[0x6A]= eicrb_reg;
490  rw[0x69]= eicra_reg;
491  rw[0x68]= pcicr_reg;
492  // 0x67 reserved
493  rw[0x66]= osccal_reg;
496  // 0x63 reserved
497  // 0x62 reserved
498  rw[0x61]= clkpr_reg;
500  rw[0x5F]= statusRegister;
501  rw[0x5E]= & ((HWStackSram *)stack)->sph_reg;
502  rw[0x5D]= & ((HWStackSram *)stack)->spl_reg;
503  rw[0x5C]= & eind->ext_reg;
504  rw[0x5B]= & rampz->ext_reg;
505  // 0x58 - 0x5A reserved
506  rw[0x57]= & spmRegister->spmcr_reg;
507  // 0x56 reserved
511  // 0x52 reserved
513  rw[0x50]= & acomp->acsr_reg;
514  // 0x4F reserved
515  rw[0x4E]= & spi->spdr_reg;
516  rw[0x4D]= & spi->spsr_reg;
517  rw[0x4C]= & spi->spcr_reg;
518  rw[0x4B]= gpior2_reg;
519  rw[0x4A]= gpior1_reg;
520  // 0x49 reserved
521  rw[0x48]= & timer0->ocrb_reg;
522  rw[0x47]= & timer0->ocra_reg;
523  rw[0x46]= & timer0->tcnt_reg;
524  rw[0x45]= & timer0->tccrb_reg;
525  rw[0x44]= & timer0->tccra_reg;
526  rw[0x43]= & gtccr_reg;
527  rw[0x42]= & eeprom->eearh_reg;
528  rw[0x41]= & eeprom->eearl_reg;
529  rw[0x40]= & eeprom->eedr_reg;
530  rw[0x3F]= & eeprom->eecr_reg;
531  rw[0x3E]= gpior0_reg;
532  rw[0x3D]= eimsk_reg;
533  rw[0x3C]= eifr_reg;
534  rw[0x3b]= pcifr_reg;
535  rw[0x3A]= & timerIrq5->tifr_reg;
536  rw[0x39]= & timerIrq4->tifr_reg;
537  rw[0x38]= & timerIrq3->tifr_reg;
538  rw[0x37]= & timerIrq2->tifr_reg;
539  rw[0x36]= & timerIrq1->tifr_reg;
540  rw[0x35]= & timerIrq0->tifr_reg;
541  rw[0x34]= & portg.port_reg;
542  rw[0x33]= & portg.ddr_reg;
543  rw[0x32]= & portg.pin_reg;
544  rw[0x31]= & portf.port_reg;
545  rw[0x30]= & portf.ddr_reg;
546  rw[0x2F]= & portf.pin_reg;
547  rw[0x2E]= & porte.port_reg;
548  rw[0x2D]= & porte.ddr_reg;
549  rw[0x2C]= & porte.pin_reg;
550  rw[0x2B]= & portd.port_reg;
551  rw[0x2A]= & portd.ddr_reg;
552  rw[0x29]= & portd.pin_reg;
553  rw[0x28]= & portc.port_reg;
554  rw[0x27]= & portc.ddr_reg;
555  rw[0x26]= & portc.pin_reg;
556  rw[0x25]= & portb.port_reg;
557  rw[0x24]= & portb.ddr_reg;
558  rw[0x23]= & portb.pin_reg;
559  rw[0x22]= & porta.port_reg;
560  rw[0x21]= & porta.ddr_reg;
561  rw[0x20]= & porta.pin_reg;
562 
563  Reset();
564 }
565 
ADC reference is selected on 3 or 4 different sources: Vcc, aref pin, bandgap or 2.56V reference.
Definition: hwad.h:60
Basic AVR device, contains the core functionality.
Definition: avrdevice.h:66
0:aref, 1:vcc, 2:bg, 3:2.56V
Definition: hwad.h:68
PrescalerMultiplexer premux2
prescaler multiplexer for timer 2
IOSpecialReg assr_reg
ASSR IO register.
IOReg< HWTimer16 > ocrc_h_reg
output compare C register, high byte
Definition: hwtimer.h:316
bool flagEIJMPInstructions
EICALL and EIJMP instructions are available (only on some devices with bigger flash) ...
Definition: avrdevice.h:118
AvrFuses * fuses
Definition: avrdevice.h:100
TimerIRQRegister * timerIrq3
timer interrupt unit for timer 3
AddressExtensionRegister * rampz
RAMPZ address extension register.
Definition: avrdevice.h:105
Pin class, handles input and output to external parts.
Definition: pin.h:98
HWIrqSystem * irqSystem
Definition: avrdevice.h:104
IOReg< HWAd > admux_reg
Definition: hwad.h:269
Implements a stack with stack register using RAM as stackarea.
Definition: hwstack.h:131
TimerIRQRegister * timerIrq4
timer interrupt unit for timer 4
IOReg< HWUart > ubrrhi_reg
IO register "UBRRxH" - baudrate.
Definition: hwuart.h:136
ExternalIRQHandler * extirqpc
external interrupt support for PCINT[0-2]
IOSpecialReg * eifr_reg
EIFR IO register.
IOReg< HWEeprom > eedr_reg
Definition: hweeprom.h:101
void registerIrq(int vector, int irqBit, ExternalIRQ *extirq)
Definition: externalirq.cpp:53
IOReg< HWTimer16 > ocra_h_reg
output compare A register, high byte
Definition: hwtimer.h:312
Implement CLKPR register.
Definition: rwmem.h:135
Pin & GetPin(unsigned char pinNo)
returns a pin reference of pin with pin number
Definition: hwport.cpp:87
oscillator version 5.x, 8bit, two ranges
Definition: rwmem.h:181
IOSpecialReg * eimsk_reg
EIMSK IO register.
IOReg< HWTimer16 > ocra_l_reg
output compare A register, low byte
Definition: hwtimer.h:313
IOReg< HWAcomp > acsr_reg
ACSR IO register.
Definition: hwacomp.h:82
IOReg< HWTimer8 > tcnt_reg
counter register
Definition: hwtimer.h:229
Definition: hwwado.h:38
A register in IO register space unrelated to any peripheral. "GPIORx" in datasheets.
Definition: rwmem.h:113
IOReg< HWTimer16 > tcnt_h_reg
counter register, high byte
Definition: hwtimer.h:310
PrescalerMultiplexerExt premux1
prescaler multiplexer for timer 1
Handler for external IRQ&#39;s to communicate with IRQ system and mask/flag registers.
Definition: externalirq.h:41
IOReg< HWTimer16 > ocrc_l_reg
output compare C register, low byte
Definition: hwtimer.h:317
Represents a timer interrupt line, Frontend for timer interrupts.
Definition: timerirq.h:42
IOSpecialReg * pcicr_reg
PCICR IO register.
void SetFuseConfiguration(int size, unsigned long defvalue)
Configure fuses.
Definition: flashprog.cpp:246
IOReg< AddressExtensionRegister > ext_reg
Definition: ioregs.h:45
IOReg< HWUart > ubrr_reg
IO register "UBRRxL" - baudrate.
Definition: hwuart.h:136
HWUsart * usart2
usart 2 unit
HWTimer16_3C * timer1
timer 1 unit
IOReg< HWTimer8_2C > tccrb_reg
control register B
Definition: hwtimer.h:440
IOSpecialReg tifr_reg
the TIFRx register
Definition: timerirq.h:74
IOReg< HWAd > adcsrb_reg
Definition: hwad.h:269
IOReg< HWSpi > spdr_reg
Definition: hwspi.h:121
Implements the I/O hardware necessary to do USART transfers.
Definition: hwuart.h:149
IOReg< HWPort > port_reg
Definition: hwport.h:84
IOReg< HWUart > ucsra_reg
Definition: hwuart.h:136
void Reset()
Definition: avrdevice.cpp:390
IOReg< HWPort > pin_reg
Definition: hwport.h:84
HWAcomp * acomp
analog compare unit
IOReg< HWTimer8_2C > tccra_reg
control register A
Definition: hwtimer.h:439
PrescalerMultiplexerExt premux0
prescaler multiplexer for timer 0
IOReg< HWTimer16 > icr_h_reg
input capture register, high byte
Definition: hwtimer.h:318
TimerIRQRegister * timerIrq2
timer interrupt unit for timer 2
IOReg< HWSpi > spcr_reg
Definition: hwspi.h:121
ADC type M2560: ADC on atmega2560.
Definition: hwad.h:266
ExternalIRQHandler * extirq
external interrupt support for INT0 to INT7
PrescalerMultiplexerExt premux4
prescaler multiplexer for timer 4
TraceValueCoreRegister coreTraceGroup
Definition: avrdevice.h:108
GPIORegister * gpior0_reg
general purpose IO register
IOReg< HWUart > ucsrb_reg
Definition: hwuart.h:136
IOReg< HWTimer16 > icr_l_reg
input capture register, low byte
Definition: hwtimer.h:319
GPIORegister * gpior2_reg
general purpose IO register
HWTimer16_3C * timer5
timer 5 unit
IOReg< HWAd > adcsra_reg
Definition: hwad.h:269
IOSpecialReg * pcmsk2_reg
PCIMSK2 IO register.
HWTimer16_3C * timer4
timer 4 unit
HWAdmux * admux
adc multiplexer unit
IOReg< HWEeprom > eearh_reg
Definition: hweeprom.h:101
OSCCALRegister * osccal_reg
OSCCAL IO register.
IOReg< HWTimer16_3C > tccra_reg
control register A
Definition: hwtimer.h:678
IOReg< HWTimer16 > tcnt_l_reg
counter register, low byte
Definition: hwtimer.h:311
PrescalerMultiplexerExt premux5
prescaler multiplexer for timer 5
ICaptureSource * inputCapture3
input capture source for timer 3
AvrDevice_atmega2560base(unsigned ram_bytes, unsigned flash_bytes, unsigned ee_bytes, unsigned nrww_start)
HWTimer16_3C * timer3
timer 3 unit
Pin * GetPin(const char *name)
Definition: avrdevice.cpp:76
IOReg< HWTimer16_3C > tccrc_reg
control register C
Definition: hwtimer.h:680
IOSpecialReg gtccr_reg
GTCCR IO register.
PrescalerMultiplexerExt premux3
prescaler multiplexer for timer 3
IOReg< HWTimer16 > ocrb_l_reg
output compare B register, low byte
Definition: hwtimer.h:315
IOSpecialReg * pcmsk1_reg
PCIMSK1 IO register.
Timer unit with 16Bit counter and 3 output compare units.
Definition: hwtimer.h:656
Provices flag and mask register for timer interrupts and connects irq lines to irqsystem.
Definition: timerirq.h:61
IOReg< HWEeprom > eecr_reg
Definition: hweeprom.h:101
TimerIRQRegister * timerIrq0
timer interrupt unit for timer 0
IOSpecialReg * eicra_reg
EICRA IO register.
HWEeprom * eeprom
Definition: avrdevice.h:102
IOSpecialReg * pcmsk0_reg
PCIMSK0 IO register.
Definition: hwspi.h:38
void registerLine(int idx, IRQLine *irq)
Definition: timerirq.cpp:88
#define AVR_REGISTER(name, class)
Definition: avrfactory.h:69
RWMemoryMember ** rw
The whole memory: R0-R31, IO, Internal RAM.
Definition: avrdevice.h:129
ICaptureSource * inputCapture1
input capture source for timer 1
TimerIRQRegister * timerIrq1
timer interrupt unit for timer 1
HWUsart * usart0
usart 0 unit
Provides the programming engine for flash self programming.
Definition: flashprog.h:38
void SetBootloaderConfig(unsigned addr, int size, int bPosBOOTSZ, int bPosBOOTRST)
Set bootloader support configuration.
Definition: flashprog.cpp:274
IOReg< HWAd > adch_reg
Definition: hwad.h:269
IOReg< HWTimer16 > ocrb_h_reg
output compare B register, high byte
Definition: hwtimer.h:314
ICaptureSource * inputCapture5
input capture source for timer 5
HWTimer8_2C * timer2
timer 2 unit
IOReg< HWSpi > spsr_reg
Definition: hwspi.h:121
IOReg< HWEeprom > eearl_reg
Definition: hweeprom.h:101
IOReg< HWAd > adcl_reg
Definition: hwad.h:269
IOReg< HWTimer8 > ocra_reg
output compare A register
Definition: hwtimer.h:230
static NotSimulatedRegister * getRegister(int reg)
Definition: rwmem.cpp:297
HWStack * stack
Definition: avrdevice.h:131
Class, which provides input capture source for 16bit timers.
Definition: icapturesrc.h:34
RWSreg * statusRegister
the memory interface for status
Definition: avrdevice.h:133
IOReg< HWUart > udr_reg
Definition: hwuart.h:136
IOReg< HWTimer16_3C > tccrb_reg
control register B
Definition: hwtimer.h:679
Timer unit with 8Bit counter and 2 output compare unit.
Definition: hwtimer.h:416
TimerIRQRegister * timerIrq5
timer interrupt unit for timer 5
Pin-change interrupt on all pins of a port.
Definition: externalirq.h:137
IRQLine * getLine(const std::string &name)
Definition: timerirq.cpp:109
HWWado * wado
WDT timer.
Definition: avrdevice.h:134
Definition: hwad.h:204
GPIORegister * gpior1_reg
general purpose IO register
IOSpecialReg * eicrb_reg
EICRB IO register.
AddressExtensionRegister * eind
EIND address extension register.
Definition: avrdevice.h:106
HWUsart * usart3
usart 3 unit
FlashProgramming * spmRegister
Definition: avrdevice.h:99
ICaptureSource * inputCapture4
input capture source for timer 4
HWARef * aref
adc reference unit
IOReg< HWTimer8 > ocrb_reg
output compare B register
Definition: hwtimer.h:231
IOReg< HWPort > ddr_reg
Definition: hwport.h:84
HWUsart * usart1
usart 1 unit
IOReg< HWUsart > ucsrc_reg
Definition: hwuart.h:173
IOSpecialReg timsk_reg
the TIMSKx register
Definition: timerirq.h:73
HWTimer8_2C * timer0
timer 0 unit
Analog comparator peripheral.
Definition: hwacomp.h:42
IOReg< FlashProgramming > spmcr_reg
Definition: flashprog.h:95
HWSpi * spi
spi unit
IOSpecialReg * pcifr_reg
PCIFR IO register.
Implement OSCCAL register.
Definition: rwmem.h:174
External interrupt (INT0, INT1...) on a single pin, one and 2 bit configuration.
Definition: externalirq.h:110
bool flagELPMInstructions
ELPM instructions are available (only on devices with bigger flash)
Definition: avrdevice.h:120
CLKPRRegister * clkpr_reg
CLKPR IO register.